Users of analog to digital converters generally wish to see high conversion accuracy and high conversion rates. These objectives are generally opposed, and become more difficult to achieve when a user also seeks for such devices to be relatively inexpensive.
Flash converters are known to provide high conversion speed, albeit at increased cost and with limited resolution. In essence a flash converter consists of a plurality of comparators, each comparator connected to a respective tap on a resistor chain such that each converter is responsible for testing for one, and only one, of the possible digital outputs. Therefore an 8 bit flash converter requires 255 individual comparators to be fabricated therein, each connected to a respective tap of a resistor chain. Each comparator compares an input signal with its respective reference signal, and then a conversion circuit is responsive to the output of each of the comparators and uses this to determine where a transition between two adjacent comparators occurs so as to provide a digital output word.
Where reduced cost and/or greater accuracy is required, then it is known to use a successive approximation converter. A successive approximation converter performs successive bit trials to see, whether, once the bit is set if the analog value that it is converting is greater or less than the equivalent value represented by the bit being trialled, and the sum of any previous kept bits. Thus, a successive approximation converter seeking to produce an 8 bit output has to perform 8 bit trials.
The paper “A Successive Double Bit Approximation Technique for Analog/Digital Conversion” Sanjay M. Bhandari and Sudhir Aggarwal, IEEE Transactions on Circuits and Systems, Vol. 37, No. 6, June 1990 discloses a converter which, in a first step, tests the most significant bits 0100, 1000 and 1100, and repeats this sequence is second and subsidiary steps. This system uses two D/A converters, one to output the current bit trial and the other to set the next most significant bit, and the outputs are added and subtracted in the analog domain to generate three decision thresholds. The double bit trial is continued to the end of the conversion. The formation of sums and differences in the analog domain could give rise to a source of conversion error. The technique was only described in the context of an 8 bit converter.
U.S. Pat. No. 6,239,734 discloses an analog to digital converter having three converters which co-operate such that each trial can determine two bits within the digital word. An example shown in FIG. 7 of U.S. Pat. No. 6,239,734 discloses the conversion of a 6 bit word where the analog input signal has a value which, when converted, corresponds to “110011”. In accordance with the normal successive approximation process, a first register is set to trial the words “100000” however a second register SAR+ is set to trial the word “110000” and a third register SAR− is set to trial the word “010000”. In this first trial, the analog value is greater than each of the trial words and hence the first two bits in the trial can be set to “11”. In the second trial the two bits being tested are set to “10, 11, and 01” in the registers, respectively, such that the first register trials a bit stream “111000” the SAR+ register trials the bit stream “111100” and the SAR− register trials the bit stream “110100” at the end of this trial the analog value is less than each of the trialled words and hence the next two bits can be set to “00”. In the third step, the process is completed when two of the trial words are less than the analog value and the third trial word is not, thereby recovering the word “11001” therefore the conversion of a six bit word is converted in three trials and in general and end bit word is converted in
  N  2trials.
Whilst the performance of the device disclosed in U.S. Pat. No. 6,239,734 looks impressive it suffers from several significant shortcomings. One of these shortcomings results from the fact that, in the real world, components and systems, are noisy, whether this noise comes via the power supply lines, or is from self generated thermal noise. In general, when a circuit designer seeks to use three successive approximation converters to do the job that previously had been done by one he can either choose to use three times the die area and sink three times as much current by repeating the original approximation converter design, or he can shrink the size of the converter by using smaller components. The first option, that is tripling the die area and the power consumption is generally not favoured as it makes the device more expensive to manufacture and less likely to be adopted by users as it eats into their power budget, which is particularly important in the context of mobile devices which are battery powered.
However simply making the individual converters smaller carries a noise penalty. This is because the thermal voltage fluctuations generated across a capacitor are proportional to
  kT  Cwhere k is Boltzmanns constant, T is the temperature in kelvin and C is the capacitance of the capacitor. It could therefore be seen that smaller capacitors have greater thermal noise appearing at their terminals. In the arrangement of U.S. Pat. No. 6,239,734 thermal noise occurring at any one of the successive approximation converters can result in that converter giving a false result and will skew the entire conversion process. Put another way, although three converters are used rather than making the converter less sensitive to thermal noise, it effectively makes it more sensitive to thermal noise. This probably does not represent an issue with the context of the 6 bit of the converter, but with modern converters requiring 12 bit or greater accuracy, the presence of noise in the real world is now a significant factor in analog to digital converter design.
An additional important shortcoming of U.S. Pat. No. 6,239,734 is that collaborative bit trials are only possible as long as the miss-match errors between collaborative conversion engines are smaller than the resolution of the converter. This may in practice limit such ADCs to about 10 bits.